Dynamic random access memory (DRAM) devices typically utilize sense amplifiers to facilitate efficient reading and writing operations. Such sense amplifiers may be referred to as input/output sense amplifiers and may be constructed in a manner similar to the sense amplifiers described in commonly assigned U.S. Pat. Nos. 5,701,268 to Lee et al. and 5,953,259 to Yoon et al., the disclosures of which are hereby incorporated herein by reference.
In multi-bank memory devices, dedicated data buses are typically provided so that data being read from a respective memory bank or written to a respective memory bank can be sensed and amplified by a dedicated group of sense amplifiers. Thus, for example, a multi-bank memory device having four banks of memory may include four dedicated data buses and four dedicated groups of sense amplifiers where each group of sense amplifiers operates on data being passed to or received from a respective memory bank. Unfortunately, the use of dedicated data buses and dedicated sense amplifiers reduces layout efficiency, particularly as the storage capacity of the memory banks increase. Accordingly, notwithstanding conventional multi-bank memory devices, there continues to be a need for improved data bus and sense amplifier circuits that can used with large memory banks and have reduced layout area requirements.